ICE40 floorplan/layout viewer

This is a Javascript application to view the floorplan/layout of an ICE40 FPGA configuration generated by project Icestorm. Particular focus is on drawing all span4 and span12 wires, to give an idea of how the actual routing of signals looks down on the chip.

Upload the target *.asc file using the file upload widget on the right. HX1K, HX8K, and UP5K designs are all supported. After a few seconds to process the input file, the result will be displayed on the main canvas. For a quick demonstration, try selecting one of the pre-defined examples.

Zooming is available using the mouse wheel, or with the "+" and "-" keys, or the slider to the right. Click+drag left mouse to pan, or use the arrow keys.

More detail is shown at deeper zoom levels. Use the detail level slider on the right to adjust the level of detail shown at a given zoom level (more detail is slower).

By hovering over a wire (on a zoom level where wires are visible), the connected nets will be high-lighted, and the name of the net will be displayed in the sidebar on the right, if a symbol was available in the *.asc file. This is very useful to see how individual signals are routed across the FPGA.

Left-clicking a wire (or pressing SPACE) will do a perma-selection of the wire under the mouse, where the selection is kept until cancelled by clicking away from any wire (or pressing the ESC key).Perma-selection is useful for large connected nets, allowing to zoom and pan while keeping the selection active. Multiple clicks/keypresses in succession will cycle through nearby wires, useful when multiple nets are really close together.

Perma-selection can also be done by selecting the desired net in the listbox on the right, if the loaded .asc file contains symbols. The filter below the listbox allows to show only symbols that contain a specified string

Tiles that contain active cells are high-lighted. LUT functions are shown as boolean expression in A, B, C, D, or as a truth-table.

Tiles are colour-coded as Logic tile, Block ram, or IO tile.

Keyboard shortcut summary:

HOMEReset zoom to default (fit entire FPGA in window)
+ (plus-sign)Zoom in
- (minus-sign)Zoom out
Left arrowPan left
Right arrowPan right
Down arrowPan down
Up arrowPan up
SpaceCycle perma-selection (same as single-click)
ESCClear perma-selection (same as clicking outside any wire)

This is work in progress, currently not all connections are shown (like global nets).

This program is Free Software, licensed under an ISC License. Source code is available on the Github page.

The examples (except "vga" and "icestick") are taken from ice40_examples on GitHub, and are licensed under GPLv3. The "icetick" example is from project Icestorm. Source code for the examples, for reference:

Contact: Kristian Nielsen <>